Click here for Word format resume
Cover Letter:
Dear Human resources/Hiring manager for Engineering jobs,
I am applying for the Electrical Engineer position in the field of
ASIC or FPGA design and verification, DFT or Application engineering.
I have a Master's degree (MSEE) in Electrical Engineering and four
years of industry experience as an ASIC design engineer. I have
worked on various stages of the design flow and have performed
functions such as RTL logic design using Verilog; design
verification; Dynamic timing analysis using TimeMill; DFT and ATPG
using Tetramax; FPGA design. I have good communication skills
and problem solving ability.
I was responsible for finding the cause of design failure when the
DSP processor communicates with the Memory. I was also responsible
for generating ATPG patterns that passed functional test in Verilog.
I am willing to self-relocate nationwide, within USA and Canada,
and my salary requirement is negotiable. You can call me at
(408) 829-2757 or (404) 431-5545 or email me at salah.kazi@gmx.net.
Sincerely,
Salahuddin (Salah) Kazi
Home1: 396 Ano Nuevo Ave, Apt# 312, Sunnyvale, CA 94085
Home2: 107 Stoneview Trail, Atlanta, GA 30047
Tel: (408) 829-2757
(404) 431-5545
Email: salah.kazi@gmx.net
Web: http://salahkazi.tripod.com/resume.htmResume:
SUMMARY
MSEE, 4 years experience, worked extensively on dynamic timing
analysis using TimeMill, designed Remote I/O expander for I2C bus,
worked on ATPG for DFT, experienced user of Verilog, TimeMill and ATPG
OBJECTIVE
To work as an Electrical Engineer in the field of ASIC, custom
or FPGA design and verification, DFT or Application engineering
WORK EXPERIENCE
Web consultant 01/02 to present
* Designed, developed and published the website for The Royal Leather (theroyalleather.com)
* Developed the website for American Impex (americanimpex.com)Agere Systems, Atlanta, GA 05/00 to 01/02
Functional design engineer
* Designing the next-generation, high-speed DSP processors
* Configured TimeMill and performed dynamic timing analysis and
solved issues on gate level netlist
* Generated ATPG vectors that passed functional test for DFT work
using Tetramax
* Pushed Verilog RTL through the design flow using Epic tools suite
by Synopsys
* Verified Verilog cell library against the Spice library using ATPG
test vectors
Fairchild Semiconductor, San Diego, CA 02/98 to 05/00
Digital Circuit design engineer
* Designed CMOS RTL logic using Verilog HDL and verified design
using Verilog-XL
* Designed and verified Remote 8-bit I/O expander for I2C bus
* Verified the isophase mode of Video decoder and determined the
offset limits for the inputs and submitted report
* Designed logic for error counter and entered schematic using ALTERA
FPGA tools
* Edited PCB layout and schematic, and developed boot sequence for board
SKILLS
Application Software (UNIX Environment)
Verilog HDL, Viewlogic VHDL, Verilog-XL, TimeMill, PathMill,
EPIC tools suite by Synopsys, Tetramax, ALTERA MAX+II, HSPICE
Programming Languages
C, Java, Pascal, FORTRAN, Assembly Language, Perl
EDUCATION (MSEE)
Oklahoma State University, Stillwater, OK
Master of Science, December 1997, Electrical Engineering
Osmania University, Hyderabad, India
Bachelor of Engineering, July 1995, Computer Science and Engineering
ACCOMPLISHMENTS (Course projects)
* Designed a 32 bit SRAM memory unit at MOSFET transistor
level and tested read and write operations using SPICE
* Designed 32-bit Fast adder, Pipeline adder and 32-bit Barrel shifter
* Designed a RISC processor using VHDL and designed and tested 32-bit
ALU, and Central Processor Unit CPU for VLSI course project
* Designed 6 bit Binary Decoder with enable, 16-bit Register cell bus
and 16-bit Multi function register using VHDL, and Magic for layout
* Designed and tested 8-bit Multiplier using Booth recoding algorithm
RELOCATION
Willing to self-relocate nationwide within USA and Canada
